As digital communication links become increasingly faster, many technical difficulties arise. One of the factors limiting the speed of a communication channel is the property of the physical electrical link, which is usually constrained by the latest electrical and integrated circuit technology to be significantly less than the desired aggregate communication speed. Therefore, it is common practice to employ a number of parallel physical communication lanes to achieve a greater aggregate logical link speed. This is known as Multi-Lane Distribution (MLD).
A problem then arises as to how the number of physical communication lanes may be re-combined when the individual high-speed lanes have been impaired by various means during their propagation from a transmitter to a receiver. The arrival time difference of the various individual lanes needs to be corrected so that the individual bits may be correctly re-assembled into the prescribed order corresponding to the aggregate link prior to transmission. For example, the bits arriving on individual lanes may have skewed arrival times due to different lengths of wire or printed circuit board (PCB) trace. The slightly different timestamps can potentially cause variation in a slave clock.
An additional problem occurs when logical lanes are multiplexed over various different types of physical lanes, e.g., electrical lanes or optical lanes. As a logical lane moves from one physical lane to another (electrical or optical), the delay of that logical lane changes since the logical lane is constrained by the delay of the physical lane that the logical lane happens to be carried on.